As shown in FIG. 1, a typical computer system 10 has, among other components, a microprocessor 12, one or more forms of memory 14, integrated circuits 16 having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths 18, e.g., wires, buses, etc., to accomplish the various tasks of the computer system 10.
Referring now to FIG. 2, in designing an integrated circuit (e.g., 16 in FIG. 1), it is first necessary to specify a desired behavior of the integrated circuit. Such a specification 20 should be sufficiently rigorous and thorough so as to define the behavior of the integrated circuit in any combination of internal and external, or output, states. This specification 20 is then characterized in a hardware description language (HDL) 22 (e.g., Verilog). The hardware description language 22 describes in a high level of abstraction the specified integrated circuit design in a technology-independent manner.
The hardware description language 22 for the integrated circuit design is then synthesized using register transfer level (RTL) design 24, which is discussed in more detail below. In the register transfer level design 24, the integrated circuit is described as a set of registers and a set of transfer functions that describe the flow of data between the registers.
The register transfer level design 24, using a circuit library 26, is then used in generating a netlist 28, or schematic of the integrated circuit. This netlist 28 is used in the design process to optimize a logic level description 30 of the integrated circuit design. The logic level optimization 30, using the circuit library 26, is used in generating another netlist 32. This netlist 32 is used in the design process to generate an actual, physical design 34 of the integrated circuit, which is then used to generate a circuit layout 36 of the specified integrated circuit design.
One important aspect of the integrated circuit design process described above with reference to FIG. 2 relates to the register transfer level design (24 in FIG. 2). A typical digital system, such as an integrated circuit (20 in FIG. 1) can be divided into data and control (e.g., finite state machine (FSM) logic) portions. The data portions collectively form a datapath and the control portion indicate to the datapath what to do and when to do it. Although the datapath has less influence on the control portion than the control portion has on the datapath, the datapath occasionally supplies values that influence a behavior of the control portion.
Register transfer level design is a means of exploiting the separation of the data and control portions in order to simplify the integrated circuit design process. Register transfer level design typically ignores the different values of the data, instead treating them as individual variables. Accordingly, register transfer level design is a hierarchical level of abstraction that is higher than gate, or logic, level design.
Register transfer level design focuses on design at the register level. Specifically, as shown in FIG. 3, register transfer level design is concerned with the transfer of variables 40, or information, among registers 42, where changes of state are dependent on clock cycles controlled by a clock signal 44. Still referring to FIG. 3, it is assumed that a clock cycle is long enough for logic 46 between the registers 42 to stabilize before a next active clock signal 44 transition.
FIG. 4 shows a typical register form 50 for a register transfer level design. In FIG. 4, the register form 50 is representative of a plurality of flip-flops 52, 54, and 56. Those skilled in the art will understand that in the typical integrated circuit design process, the arrangement and schematic of the plurality of flip-flops 52, 54, and 56 are generated using the previously designed register form 50. As shown in FIG. 4, the register form 50 is dependent on information 58 (operatively from another register) and a clock signal 60 that controls the flow and state of information through the register form 50.